Impact of Interconnection Network Resources on CMP Performance

International Worshop on Interconnection Network Architectures: On-Chip, Multi-Chip


The main goal of this work is to analyze the tradeoffs when devoting more or less CMP system resources to the interconnection network. This preliminary study explores the effects that the resources (mainly buffer room and topology) have on the performance of a chip multiprocessor organized as a SNUCA. Results show that lowering throughput from 0.43 to 0.17 phits/cycle/router increases execution time by 25% on average. This provokes a reduction of approximately 30% in interconnection network power, but at the cost of increasing the energy consumed by the whole CMP system by 25%.