Topology-aware CMP design

Interconnection Network Architectures: On-Chip, Multi-Chip.


This paper attempts to describe the impact of some architectural decisions, such as interconnection network topology and processor placement, on global system performance of a Chip Multi-processor (CMP). By utilizing different layout options, we evaluate the behavior of the system in a real environment, running scientific and commercial applications. We discuss the results obtained considering technological restrictions and suggest the use of folded torus topologies as a substitute for meshes. Then we provide an ad-hoc implementable architecture that outperforms classical mesh topologies with boundary placed processors, maintaining technological restrictions.