Evaluating Kilo-instruction Multiprocessors

Workshop on Memory Performance Issues


The ever increasing gap in processor and memory speeds has a very negative impact on performance. One possible solu- tion to overcome this problem is the Kilo-instruction proces- sor. It is a recent proposed architecture able to hide large memory latencies by having thousands of in-flight instruc- tions. Current multiprocessor systems also have to deal with this increasing memory latency while facing other sources of latencies: those coming from communication among proces- sors. What we propose, in this paper, is the use of Kilo-in- struction processors as computing nodes for small-scale CC- NUMA multiprocessors. We evaluate what we appropriately call Kilo-instruction Multiprocessors. This kind of systems appears to achieve very good performance while showing two interesting behaviours. First, the great amount of in- flight instructions makes the system not just to hide the latencies coming from the memory accesses but also the in- herent communication latencies involved in remote memory accesses. Second, the significant pressure imposed by many in-flight instructions translates into a very high contention for the interconnection network, what indicates us that more efforts need to be employed in designing routers capable of managing high traffic levels.